1. Field of the Invention
The present invention relate to an AD converter converting analogue input voltage to digital signals and, more specifically, it relates to a serial-parallel type AD converter capable of high speed operation having an enlarged analogue input band.
2. Description of the Prior Art
FIG. 1 is a block diagram showing one example of the conventional serial-parallel type AD converter disclosed in, for example, a catalog of Micro Power Systems Incorporated, "One Chip 11 Bit CMOS Flash A/D Converter MP7685 Long Desired in the Industry". FIG. 1 shows an AD converter of 4 bit structure.
The A/D converter is constituted by a first parallel type AD converting portion 1 for determining higher order bits of the digital output, and a second parallel type AD converting portion 2 for determining lower order bits thereof.
The first parallel type AD converting portion 1 comprises three first voltage comparators CC1.about.CC3, a first determining circuit J1, a first encoder E1 and a first reference voltage generating circuit RG comprising resistances R1.about.R16 and a constant voltage source 3. The second parallel type AD converting portion is constituted by three second voltage comparators FC1.about.FC3, a second determining circuit J2, a second encoder E2 and a switch control circuit SCC forming a second reference voltage generating circuit. The switch control circuit SCC comprises switches S1.about.S12 connected to the first reference voltage generating circuit RG comprising the resistances R1.about.R16 and a constant voltage source 3.
In the first parallel type AD converting portion 1, the voltage V11 generated between the resistances R4 and R5, the voltage V12 generated between the resistances R8 and R9, and the voltage V13 generated between the resistances R12 and R13 are respectively supplied to the first voltage comparators CC1.about.CC3 as reference voltages. In the second parallel type AD converting portion, voltages obtained from respective nodes between the serially connected resistances R1.about.R16 through the switches S1.about.S12 forming the switch control circuit SCC are respectively applied to the second voltage comparators FC1.about.FC3 as reference voltages V21, V22 and V23. The reference voltage V21 is provided from one of the switches S1, S4, S7 and S10; the reference voltage V22 is provided from one of the switches S2, S5, S8 and S11; and the reference voltage V23 is provided from one of the switches S3, S6, S9 and S12.
The resistances R1.about.R16 are divided into four resistance groups RG1.about.RG4, respectively constituted by resistances R1.about.R4, resistances R5.about.R8, resistances R9.about.R12 and resistances R13.about.R16. In correspondence with the resistance groups RG1.about.RG4, the switches S1.about.S12 are divided into four switch groups SG1.about.SG4, respectively constituted by switches S1.about.S3, switches S4.about.S6, switches S7.about.S9 and switches S10.about.S12. One of the switch groups SG1.about.SG4 operates in response to a signal from the first determining circuit J1 at the first parallel type AD converting portion 1. Consequently, reference voltages V21, V22 and V23 are respectively supplied to the second voltage comparators FC1.about.FC3.
FIG. 2A is a circuit diagram showing one example of a definite structure of each of the first voltage comparators CC1.about.CC3 shown in FIG. 1.
Each of the voltage comparators CC1.about.CC3 comprises an input stage I, an amplifying stage Z and a latch stage L. One input terminal 4 of the input stage 1 receives an analogue input voltage and the other input terminal 5 receives ay one of the reference voltages V11, V12 and V13. The input terminal 4 is connected to one electrode of a coupling capacitance 6 through the switch S13 which turns on/off in response to a clock signal .phi.1 The input terminal 5 is connected to the same electrode of the coupling capacitance 6 through the switch S14 which turns on/off in response to a clock signal .phi.1. The other electrode of the coupling capacitance 6 is connected to an input terminal of an inverting amplifier 7. The inverting amplifier 7 has its output terminal connected to the input terminal of itself through the switch S15 which turns on/off in response to a clock signal .phi.2. The output terminal of the inverting amplifier is also connected to an input terminal of an inverting amplifier 8 in the succeeding stage. The inverting amplifier 8 has its output terminal connected to an input terminal of an inverting amplifier 9 through the switch 16 which turns on/off in response to a clock signal .phi.2. The output terminal of the inverting amplifier is also connected to an input terminal of an inverting amplifier 10 of the succeeding stage. An output terminal of the inverting amplifier 10 is connected to an output terminal 11 and is fed back to the input terminal of the inverting amplifier 9 through the switch S17 which turns on/off in response to the clock signal .phi.2.
FIG. 2B is a circuit diagram showing one example of a definite structure of the second voltage comparators FCl.about.FC3 shown in FIG. 1.
The circuit structure of the voltage comparators FC1.about.FC3 is almost the same as that of the voltage comparators CC1.about.CC3 shown in FIG. 2A. The switches S18.about.S21 correspond to the switches S13, S15.about.S17 of FIG. 2A, and the inverting amplifiers 13.about.16 correspond to the inverting amplifiers 7.about.10 of FIG. 2A. The coupling capacitance 12 corresponds to the coupling capacitance 6 of FIG. 2,, the input terminal 18 corresponds to the input terminal 5 of FIG. 2A, and the output terminal 17 corresponds to the output terminal 11 of FIG. 2A. Different from the circuit of FIG. 2A, one of the reference voltages V21, V22 and V23 is applied to the input terminal 18. The input terminal 18 is directly connected to the coupling capacitance 12 and not through the switch S14 as shown in FIG. 2A. The switches S18, S19 and S21 turn on/off in response to the clock signal .phi.1, and the switch 20 turns on/off in response to the clock signal .phi.1.
The AD converter shown in FIG. 1 operates as described in the following.
Referring to FIG. 1, when an analog input voltage Vin is inputted to the input terminal 4, the analog input voltage Vin is compared with the reference voltages V11, v2 and V13 respectively by the first voltage comparators CC1.about.CC3. When the analog input voltage Vin is midway between the reference voltages V11 and V12, for example, the output from the voltage comparators CC2 and CC3 become "L" level, and the output from the voltage comparator CC1 becomes "H" level. The output data are inputted to the first determining circuit J1. Consequently, the output of the first determining circuit J1 will be "0", "0", "1" and "0". The output from the first determining circuit J1 are encoded by the first encoder (encoding circuit) E1. Thus the first AD conversion of the analog input voltage Vin to digital code is carried out.
Thereafter, the switches S4.about.S6 of the switch group SG2 provided between the reference voltages V11 and V12 are turned on in response to the signal from the first determining circuit J1. Consequently, reference voltages V21, V22 and V23 are respectively applied to the second voltage comparators FCl.about.FC3. The analog input voltage Vin is compared with the reference voltages V21, V22 and V23 respectively by the voltage comparators FC1.about.FC3. When the analog input voltage Vin exists between the reference voltage V21 and V22, for example, the outputs of the voltage comparators FC2 and FC3 become "L" level, and the output of the voltage comparator FC1 becomes "H" level. The output data of the voltage comparators FC1.about.FC3 are inputted to the second determining circuit J2, and the output of the second determining circuit J2 will be "0", "0", "1" and "0". The outputs from the second determining circuit J2 are encoded in the second encoder E2. Thus the second AD conversion is carried out.
The principle of operation of the first voltage comparators CCj (j=1.about.3) (FIG. 2A) in the above operation will be described in the following.
As shown in a timing chart of FIG. 3A, while the clock signals .phi.1 and .phi.2 are at "H" level, the switch S14, S15 and S17 are on, and the switches S13 and S16 are off. In this case, a short circuit is generated between the input terminal and the output terminal of the inverting amplifier 7 in the amplifying stage Z, and the inverting amplifier 7 is biased to a certain potential V.sub.B1. The potential biased in this manner will be hereinafter referred to as "balance potential". The above described operation mode in the amplifying stage Z will be referred to as "auto zero mode". Therefore, in the auto zero mode, the coupling capacitance 6 is charged by any one of the reference voltages V11.about.V13 applied to the input terminal and the balance potential VB1 of the inverting amplifier 7. Since the switch S16 is off at this time, the amplifying stage Z and the latch stage L are cut off from each other.
While the clock signals .phi.1 and .phi.2 are at "L" level and the complementary clock signals .phi.1 and .phi.2 are at the "H" level, the switches S13 and S16 are on, the switches S14, S15 and S17 are off. On this occasion, the analog input voltage Vin is applied from the input terminal 4 to the input side electrode of the coupling capacitance 6. Since the switch S15 is off, the flowing in and out of charges to and from the path of the switch S15 are prevented, and the charges stored in the auto zero mode are reserved. Therefore, the change of voltage from the reference voltage take place at the input side electrode of the coupling capacitance 6 is transmitted to the output side electrode of the coupling capacitance 6 with correct polarization, provided that there is no error caused by clock noise or the like, and the voltage amplitude from the balance potential is amplified by inverting amplifiers 7 and 8. This operation mode of the amplifying stage Z will be hereinafter referred to as "comparing mode". The change of the voltage amplified by the amplifying stage Z is applied to the latch stage L through the switch S16, and it is further amplified by two inverting amplifiers 9 and 10. This operation of the latch stage will be hereinafter referred to as "through mode".
When the clock signals .phi.1 and .phi.2 again become "H" level, the switch S16 turns off and the switch S17 turns on. The amplifying stage Z enters auto zero mode. On this occasion, the amplified input voltage change is fedback to the input terminal of the inverting amplifier 9 through the switch S17 to be latched. This operation of the latch stage L will be hereinafter referred to as "latch mode". In this manner, in the latch mode, the input voltage change is amplified so large as to enable the output of the latch stage L to reach the logic level, and it is outputted as a digital value. Namely, the magnitude of the analog input voltage Vin is compared with the magnitude of each of the reference voltages V11.about.V13, with the result of comparison outputted as a digital value.
The principle of operation of the second voltage convertors FCj (J=1.about.3) (FIG. 2B) will be described in the following with reference to the timing chart of FIG. 3B.
The principle of operation of the second voltage comparators FCj shown in FIG. 2B is the same as that of the first voltage comparators CCj shown in FIG. 2A except for the operation timing of each operation mode. More specifically, in the case of the second voltage comparators FCj, the analog input voltage Vin is taken in from the input terminal 4 while the clock signal .phi.1 is at "H" level, that is, the clock signal .phi.1 is at "L" level. At that time, the amplifying stage Z enters the auto zero mode, and the latch stage L enters the latch mode. While the clock signal .phi.1 is at the "H" level, the amplifying stage Z is in the comparing mode, and the latch stag L is in the through mode.
The reference voltages V21.about.V23 to be applied to the second voltage comparators FCj are applied to the input terminal 18 only during the period when the clock signal .phi.2 is at "H" level. This operation is effected in the following manner. Namely, a control signal applied from the first determining circuit J1 shown in FIG. 1 to the switch groups SG1.about.SG4 is controlled by the clock signal .phi.2 applied to the first determining circuit J1. Therefore, one of the switch groups SG1.about.SG4 is turned on only when the clock signal .phi.2 is in the "H" level, and all switches S1.about.S12 are off while the clock signal .phi.2 is at the "L" level.
In this manner, it is detected that the analog input voltage Vin is between the reference voltage V11 and V12, for example, and a higher order bit digital code is provided in the first parallel type AD converting portion 1. Thereafter, since the switch group SG2 is turned on, the AD conversion for obtaining higher resolution is carried out in the second parallel type AD converting portion 2. The lower order bit digital code can be provided therefrom.
As described above, the reference voltage to be applied to the second parallel type AD converting portion 2 cannot be obtained until the comparing operation of the first parallel type AD converting portion 1 is completed. Therefore, the timing of the operation mode of the second voltage comparators FCj included in the second parallel type AD converting portion 2 (FIG. 3B) is different from that of the first comparators CCj included in the first parallel type AD converting portion 1 (FIG. 3A).
Actually, the analog input voltage Vin changes at random, causing skew, that is, off set of timing, generated in sampling the analog input voltage Vin in the first and second parallel type AD converting portions 1 and 2. The samplings skew degrades the performance precision of the AD convertor. This problem will be described in the following.
The first voltage comparator CCj included in the first parallel type AD convertor 1 is in the comparing mode during sampling of the analog input voltage Vin from the input terminal 4, as shown in FIG. 3A. Namely, the switches S15 and S17 are turned off and the switch S16 is turned on. Consequently, the change in the analog input voltage Vin is transmitted to the latch stage L with some delay T1 derived from the coupling capacitance 6 and from the inverting amplifiers 7.about.10. More specifically, the analog input voltage Vin sampled at the time t0 is latched in the latch stage L at the time t2. The conversion to the digital code in the first parallel type AD converting portion 1 is carried out based on the result of comparison of the analog input voltage Vin reached the latch stage L reference voltages B11.about.B13. Therefore, the analog input voltage Vin sampled at the time t0 is converted into the digital code at the time t2.
On the contrary, the second voltage comparator FCj included in the second parallel type AD converting portion 2 enters the auto zero mode during sampling of the analog input voltage Vin from the input terminal 4, as shown in FIG. 3B. Namely, the switches S19 and S21 turn on, while the switch S20 turns off. Consequently, an input side node of the coupling capacitance 12 changes along the change of the analog input voltage Vin. A relatively small delay is incidental to the change. Therefore, in the second parallel type AD converting portion 2, the analog input voltage Vin applied at the time t2 when the switch S18 of the second voltage comparator FCj is turned off is converted into the digital code. The time of sampling of the analog input voltage Vin which is to be actually converted to the digital code at the first parallel type AD converting portion 1 and at the second parallel type AD converting portion 2 is shifted by the above mentioned delay time T1. For example, when a ramp wave having the frequency of 5 MHz is applied as the analog input voltage Vin and the delay time T1 is assumed to be 10 NS, the sampling point of the analog input voltage Vin which is actually converted into the digital code in the first parallel type AD converting portion and in the second parallel type AD converting portion 2 differs from each other by 10 ns. The difference is represented by the voltage value of 12.8 LSB, and therefore, the data different from each other by 12.8 LSB are sampled.
In an actual serial-parallel type AD convertor, timing adjustment is carried out by, for example, shifting the timing of turning off the switch S13 and the timing of turning off the switch S16 in the first voltage comparator CCj (FIG. 2A) by the time Td (=T1) as shown in the timing charge of FIG. 4, whereby the skew in sampling analog input voltage Vin between the first and second parallel type AD converting portion 1 and 2 can be compensated for.
In a conventional AD convertor, the sampling skew of the analog input voltage Vin is corrected only by the shifting the timing of latch in the first voltage comparator CCj included in the first parallel type AD converting portion 1.
However, when the time td is large, the time period in which the clock signal .phi.2 is at "H" level is reduced. The second voltage comparator FCj of the second parallel type Ad convertor portion 2 must effect the comparing mode in the short period. However, actually the second voltage comparator FCj requires a relatively long period of time to effect the comparing mode. Therefore, in order to provide enough time td the frequencies of the clock signals .phi.1 and .phi.2 must be lowered. Consequently, in the above described method of correcting skew in sampling analog input voltage Vin by shifting the timing of the clock signals is disadvantages in increasing the speed of conversion of the AD convertor and in the enlargement of the analog input band.